(1) Field of the Invention
The present invention relates to the fabrication of integrated circuits, and more particularly to a method for forming planarized shallow trenches across the semiconductor substrate (wafer) using a gradient-doped polysilicon trench fill and a chemical-mechanical polish back.
(2) Description of the Prior Art
Field oxide isolation is used to electrically isolate the discrete devices on semiconductor substrates for Ultra Large Scale Integration (ULSI). Typically a LOCal Oxidation of Silicon (LOCOS) is used in the semiconductor industry in which a patterned oxidation barrier mask (silicon nitride) is used and the silicon substrate is selectively oxidized. This results in long thermal budgets and in lateral oxidation under the barrier mask that limit the minimum spacing between adjacent active device areas and therefore prevents further increases in device packing densities. Also, as minimum feature sizes are further reduced, it is necessary to maintain a planar surface for exposing the higher resolution photoresist etch mask patterns, since the higher resolution induces a much shallower depth of focus (DOF). Also, the planarity is necessary for anisotropic plasma etching distortion-free patterned structures without residue in the overlying conductive and insulating layers that are later formed on the substrate. Since the expansion of the oxide in the vertical upward direction by the LOCOS method results in a more uneven topography, there is a strong desire to explore alternate isolation methods.
One method being explored as a replacement for the conventional LOCOS isolation is the shallow trench isolation (STI) depicted in FIGS. 1 through 5. This STI method minimizes the thermal budget, minimizes spacing between adjacent active device areas, and provides a more planar surface. The method involves filling the trenches with an oxide or undoped polysilicon which is then chemical/mechanically polished (CMP) back to form a planar structure. As shown starting with FIG. 1, the method involves growing a stress-release first thermal oxide 12 on a silicon substrate 10 and depositing a silicon nitride layer 14. Conventional photolithographic techniques and anisotropic plasma etching are used to define a photoresist mask 16 and to etch the trenches 2 in the substrate 10 where the field oxide isolation is required. As shown in FIG. 2, after removing the photoresist 16, a second thermal oxide 18 is grown on the exposed silicon surface in the trenches 2 to eliminate plasma etch damage, while the silicon nitride layer 14 prevents the oxidation of the top surface of the silicon substrate where the active device areas for fabricating the semiconductor devices are required. Next, as shown in FIG. 3, a conformal undoped polysilicon layer 20 is deposited to fill the trenches 2 (alternatively a silicon oxide (SiO.sub.2) can be used). The undoped polysilicon layer 20 is then planarized by chemical/mechanical polishing back to the silicon nitride layer 14, as shown in FIG. 4 to form the polysilicon-filled trenches 3. Finally, as shown in FIG. 5, the silicon nitride layer 14 is removed by etching in a hot phosphoric acid (H.sub.3 PO.sub.4) wet etch, and the first thermal oxide 12 is removed by wet etching in a buffered oxide etch (BOE) to complete the shallow trench isolation 3 surrounding the device areas on the substrate on and in which the devices are built.
The most important step in this conventional process is the polishing back according to the nature of chemical/mechanical polishing (CMP). Usually, different polishing rates cause the non-uniformity across the wafer. Moreover, the different removal rates between the filling material and the stop layer result in dishing 4, as shown in FIG. 4. Large differences in selectivity have a more serious dishing problem. Therefore, there are several disadvantages to this conventional method for using both silicon oxide and polysilicon trench filling. First, if a silicon oxide is used to fill the trenches, then an over-polishing step is necessary to ensure the silicon oxide layer has been removed completely, or the silicon nitride will not be etched out due to the residual oxide. However, there is a difficulty in the detection of endpoint because the polish back is not very highly selective to the underlying silicon nitride layer 14 (about 3:1 to 5:1), therefore, it can result in substrate damage. Thus, the time-mode control has been used instead of endpoint control in the conventional process.
The undoped polysilicon-filled trench not only results in a much better polish-back selectivity to the silicon nitride layer 14 (about 25:1), but also the latitude of process window for overpolish is enlarged. Also, the endpoint signal is much stronger, so the endpoint control is feasible. However, it also causes a more severe dishing in the wide trenches.
One method of improving the polish-back uniformity across the wafer for forming planarized dielectric layers for intermetal dielectrics (IMD) over the interconnecting conductive lines is described by Meikle et al. in U.S. Pat No. 5,449,314. The method employs a gradient-doped silicon oxide insulating layer which is then chemical/mechanically polished back. The chemical/mechanical polishing removes relatively fast the heavily doped elevated portions while removing more slowly the lightly doped regions resulting in a more global planarity across the wafer. However, Meikle does not teach or suggest the method for making STI regions on a substrate, and does not teach the use of a polysilicon for filling trenches.
Although there are a number of methods for forming shallow trenches and for planarizing dielectric layers, there is still a strong need to provide improved methods for forming shallow trenches with large overpolishing process window, an obvious endpoint, no dishing, and having a more planar surface with improved global planarity.